Aa far as I’m aware, incremental synthesis is vivado trying to build a new FPGA bitstream by modifying a snapshot of the previous build, to ostensibly save time. Because the SID FPGA implementation is a relatively small part of the MEGA65 core, it really likes to forget to add any changes I make, especially related to timing optimization (it took me so long to figure out it had re-enabled itself, after disabling it my total negative slack was cut in half due to it finally registering all the pipelining and other optimization). I’ve also had vivado outright lock up with some cases.